Design & Verification of a 2-Bit Mini System-on-Chip (SoC)

Domain & Tools:

Domain: Digital IC Design / VLSI
Language: Verilog HDL
Simulation Tools: Icarus Verilog (iverilog), ModelSim, GTKWave
Repository: [https://github.com/sushant18-404/mini_soc](https://github.com/sushant18-404/mini_soc)

Project Body / Extended Description:

1. Overview

This project focuses on the design, hardware modeling, and functional verification of a 2-bit System-on-Chip (SoC) architecture implemented in Verilog HDL. The system brings together core digital design building blocks—including an Arithmetic Logic Unit (ALU), a sequential state Counter, and a Multiplexer (MUX)—to form an automated, sequenced processing engine.

2. Hardware Architecture & Components

2-Bit ALU Engine: Serves as the central execution core, performing arithmetic operations (ADD, SUB) and bitwise logical operations (AND, OR, XOR, NOT) based on opcode selection.
Instruction / State Counter: A 2-bit sequential counter that steps through processing states on clock edges, enabling automated sequence generation.
Multiplexer (MUX) Control Path: Dynamically routes input operands, control lines, and data paths to the ALU based on select logic.
Status Flags Logic: Generates real-time execution condition flags:
- Zero Flag (Z): Asserts high (1) when the ALU result is 00.
- Carry Flag (C): Captures arithmetic carry/overflow conditions during operations.

3. Verification & Simulation

The design was verified using modular self-checking Verilog testbenches. The compiled output was simulated using Icarus Verilog, and the functional timing and signal transitions across clock edges were validated using GTKWave waveform analysis.

4. Engineering Impact

This project demonstrates key VLSI design principles, including modular datapath synthesis, control-path multiplexing, hardware flag generation, and RTL simulation practices.