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Design and Analysis of Current-Starved Voltage-Controlled Ring Oscillator (VCRO)

Overview

This project focuses on the design and analysis of a Current-Starved Voltage-Controlled Ring Oscillator (VCRO) using Cadence Virtuoso in 45 nm GPDK CMOS technology. The objective was to achieve a high-speed, low-power oscillator with a wide frequency tuning range suitable for analog and mixed-signal VLSI applications.

Tools & Technology

Cadence Virtuoso

GPDK045 (45 nm CMOS)

Analog Design Environment (ADE)

Key Features

Designed and simulated Current-Starved VCRO.

Performed DC, Transient, Frequency, Parametric, KVCO, PSS, Phase Noise, and Average Power analyses.

Evaluated oscillator performance over a 0.2 V–1.2 V control-voltage range.

Achieved maximum oscillation frequencies of 20.97 GHz and 5.91 GHz.

Optimized transistor sizing to improve frequency tuning, oscillation stability, and power efficiency.

Outcome

The project provided practical experience in analog VLSI design, CMOS circuit design, analog simulation, and performance optimization using industry-standard EDA tools. It strengthened my understanding of oscillator design, frequency tuning, and low-power circuit techniques.